Reactive Power Imbalances in LC VCOs and their Influence on Phase Noise Mechanisms

Phase-noise mechanisms in cross-coupled LC voltage-controlled oscillators (VCOs) are reviewed based on a physical understanding of reactive power imbalances in the tank and in the active part. These phenomena are proven to be the predominant phase-noise degradation mechanism in relatively low- and high-current operations. Based on this analysis, a technique to suppress these detrimental effects is developed and implemented in an LC VCO design. The measured results confirm the dependencies predicted by the analysis, and the usefulness of the proposed technique to simultaneously optimize the phase noise at high and low offset frequencies. The measured VCO tuning range is 600 MHz, ranging from 2.4 to 3 GHz. The VCO-prescaler circuit exhibits a phase noise from - 88 to -92 dBc/Hz at 15 kHz and from -155 to -160 dBc/Hz at 10 MHz, when the power consumption is 6 and 10 mA for the VCO and 2 mA for the prescaler, and the power supply is 2 V

On Gm-boosting and cyclostationary noise mechanisms in low-voltage CMOS differential Colpitts VCOs

This paper presents a theoretical study of CMOS differential Colpitts VCOs. The objective is to provide a deep understanding of the different mechanisms that impact the performances of these VCOs, namely the Gm-boosting and cyclostationary noise. The developed methodology and expressions can be used to analyze, optimize and build new VCO topologies. A novel topology with an optimized gate to source (GS) feedback is proposed. It exhibits a figure of merit (FOM) better than -190 dBc/Hz/mW for all the frequency offsets

A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system

A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD), and WLAN (802.11a/b/g) standards is developed. The implementation is achieved in 0.25-mum BiCMOS-SiGe process. The measured tuning range is higher that 1 GHz (3.05 to 4.1 GHz) exceeding the specifications by 25%. The voltage-controlled oscillator (VCO) exhibits a phase noise of -118 and -125 dBc/Hz measured, respectively, at 400 kHz and 1 MHz offsets while drawing 2.5 mA from 2.5 V supply. The measured phase noise at 400 kHz offset of the PCS/DCS output local-oscillator (LO) signal and the GSM output LO signal is, respectively, -124 dBc/Hz and -130 dBc/H

Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs

The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated

Contribution à l'amélioration de méthodes de caractérisations électriques de structures MIS (Au/BN/InP) et MOS

The control of the electrical properties of MIS systems is an important step for the development of MISFET devices. The aim of the present work is to improve the electrical characterisation techniques for MIS structures. In the first section of this thesis, the electrical performance of MIS capacitors made on n-type InP substrates, with boron nitride as an insulator (Au/BN/InP), has been studied. RF and microwave plasma-enhanced CVD (PECVD) techniques are used for the deposition of the dielectric. It is shown that some observed anomalies (essentially : the impurity redistribution in the substrate and mobile charges in the insulator) often affect interface states distributions evaluated by conventional capacitance methods. To avoid these limitations, we have developed a new method, based on modified BTS (bias temperature stress) measurements, to determine the density of interface traps D(it). The interface states distributions obtained by this technique have been compared to those obtained from capacitance-voltage (terman analysis) and DLTS measurements. We have then examined the influence to interface states in doping profile determination. An adaptation of the capacitance method, allowing the elimination of the profile distortion due to this influence, has been proposed. Furthermore it has been shown our method we can determine the signs and concentrations of mobile and fixed charges in the insulator. The observed frequency dispersion phenomena have been discussed. In the second section, we propose a new method to determine the surface doping concentration N(s), and flat-band voltage Vfb, for implanted MOS (SiO2/Si) structures. A technique to extract the insulator capacitance Ci, from C-V characteristics near flat band conditions, is also proposed. This research is motived by the trend to scale MOSFET's to deep submicron channel length, which increases the accuracy needed in modelling and measurement of these devices. Our methods are illustrated and validated by application on simulated MOS structures, using the 2D devices simulator ATLAS II (PISCES version of SILVACO)Le contrôle des propriétés électriques des structures mis est une étape primordiale dans le développement de la filière misfet. Le présent travail s'inscrit dans le contexte général de l'amélioration des méthodes de caractérisation des structures MIS. La première partie de la thèse concerne des structures MIS (au/bn/inp) élaborées par dépôt chimique en phase vapeur assisté par plasma rf ou micro-onde (pecvd). Une étude préliminaire de ces structures a révélé l'existence de certaines anomalies (essentiellement : la variation du profil de dopage dans le substrat et la présence de charges mobiles dans l'isolant) qui rendent souvent problématique l'évaluation de la distribution des états d'interface par les méthodes capacitives classiques. Nous avons mis au point une méthode, dite méthode BTS modifiée (contrainte tension température), qui permet de s'affranchir de ces problèmes, conduisant à une évaluation plus précise de la densité des états d'interface. Les résultats obtenus par cette méthode BTS modifiée sont comparés à ceux déduits des caractéristiques capacité-tension (analyse de terman) et des mesures DLTS. Nous avons examiné ensuite l'influence, néfaste, des états d'interface sur la détermination du profil de dopage des structures MIS. Une adaptation de la méthode capacitive, permettant de minimiser cette influence, a été proposée. De plus, nous avons montré qu'à l'aide de cette même technique on peut déterminer simultanément les densités et les signes des charges fixes et mobiles dans l'isolant, le phénomène de dispersion fréquentielle qui affecte nos mesures c-v a été aussi étudié. Dans la deuxième partie, nous proposons une nouvelles méthode pour déterminer la concentration n#s des atomes de dopage en surface et la tension de bande plates v#f#b, pour des structures MOS (SiO2/Si) implantées. D'autre part nous proposons une nouvelle approche permettant d'extraire la capacité de l'isolant des structures mos submicroniques, à partir de mesures capacitives au voisinage du régime de bandes plates. Cette recherche est motivée par la tendance actuelle à la miniaturisation extrême de ces dispositifs, qui a augmenté le besoin de développer la précision des méthodes permettant leur caractérisation. Nos méthodes ont été appliquées et validées sur des structures simulées par le logiciel atlas ii (version pisces de silvaco

Multistandard carrier generation system for quad-band GSM/WCDMA (FDD-TDD)/WLAN (802.11 a-b-g) radio

A compact carrier generation system enabling proper interoperability among quad-band GSM, WCDMA (FDD and TDD) and WLAN (802.11a/b/g) standard is developed. The implementation is achieved in 0.25μm BiCMOS-SiGe process. The measured tuning range is higher than 1GHz (3.05GHz to 4.1 GHz) exceeding by 25% the specifications. The VCO exhibits a phase noise of -118 and -125 dBc/Hz measured respectively at 400KHz and 1MHz offsets while drawing only 2.5 mA from 2.5 V supply. The measured phase noise at 400 KHz offset from the PCS 1900/DCS1800 and the GSM850/900 carriers are respectively -124 dBc/Hz and -130dBc/Hz

LC-VCO Design With Dual-Gm, Boosted for RF Oscillation and Attenuated for LF Noise

A VCO topology with a high gm at RF and low gm at low frequencies (LF) is presented. A high gm(RF) improves start-up conditions, and a low gm(LF) enables a significant improvement of the phase noise and the power supply rejection. The VCO with a modified prescaler was implemented in 0.25 mu m CMOS technology. The measured phase is -128.5 dBc/Hz at 1 MH offset, when the VCO works at 3 GHz and consumes 7.5 mW. The corresponding figure of merit is 189.2 dBc/Hz/mW

Analogue self-calibration method and apparatus for low noise, fast and wide-locking range phase locked loop

A method and apparatus for a fast and automatic setting of the phase locked loop (PLL) output frequency that significantly improves linearity, locking range as well as spectrum purity, jitter and phase noise performances is disclosed. I n one embodiment, a PLL frequency synthesizer is disclosed having a reconfigurable voltage controlled oscillator VCO with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During a first tuning operation, the VCO work in a linear high gain mode, enabling a totally analogue self-calibration of the PLL over a wide frequency tuning range and with a fast settling time. During this operation the control voltage at the input of the VCO is varied by the PLL until the appropriate output frequency is found. A method for providing a linear variation of the frequency over all the voltage tuning range during this mode is disclosed. When the loop is locked, the VCO is automatically switched to the Zero-gain mode while keeping its frequency unchanged. Its sensitivity to the noise in the control path is then practically eliminated and its phase noise performances significantly improved. If the frequency error and phase noise are sufficiently small for the considered application the tuning is stopped. If the error and phase noise are not sufficiently small the VCO is switched .again to Low-gain mode and fine-tuning adjustment of the output frequency is achieved

Phase noise in bipolar and CMOS VCO's - an analytical comparison

As RF IC design has become more prevalent and more demanding, the need for a more precise VCO phase noise model has arisen. For both MOS and bipolar VCO's new formulas are still being proposed to model the phase noise, which is a key factor for a precise oscillator. In this paper, a previous phase noise model for a bipolar VCO as presented in A. Tasic and W. A. Serdijn (2002) is refuted and the formulas developed for MOS VCO phase noise calculations based in J. J. Rael and A. Abidi (2000) are adapted to bipolar VCO. Then, the results are compared and some conclusions are drawn for the comparison of these oscillator

A Zero Capacitive LINC Architecture for Efficient Broadband Transmitters

A new approach for linear amplification with nonlinear components (Z-LINC) that provides a zero capacitive load to their power amplifiers is proposed. The zero capacitive loading over the whole power back-off range enables to overcome the efficiency deterioration. The concept is theoretically and experimentally validated through a comparative study between fabricated classical LINC and Z-LINC prototypes